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debug-tb
Debug SystemVerilog testbench failures in the SVC project. Use when a testbench fails (make _tb), to analyze CHECK_* assertion failures, watchdog timeouts, or unexpected signal values. Provides systematic debug...
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7收录技能的仓库 Stars 合计
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0同一仓库中的多个技能可能共享 Stars，合计包含重复仓库数据。
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adding-formal
Provides ASSERT/ASSUME macro pattern, .sby file template, and f_past_valid usage. Triggers when adding formal verification or writing assertions.
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GitHub
writing-sv
Provides SVC naming conventions, comment style, code structure order, and reset patterns. Triggers when writing or modifying any .sv file.
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GitHub
writing-module
Provides module template with include guard, port ordering, and checklist. Triggers when creating a new svc_ module from scratch.
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GitHub
writing-tb
Provides svc_unit.sv testbench framework, macros (TEST_CLK_NS, CHECK_EQ, etc.), and template. Triggers when creating or modifying _tb.sv files.
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GitHub
implementing-valid-ready
Provides SVC-specific valid/ready streaming interface patterns and common pitfalls. Triggers when implementing valid/ready handshakes or debugging backpressure issues.
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GitHub
implementing-axi
Provides SVC-specific AXI/AXI-Lite naming conventions, signal ordering, and available modules. Triggers when implementing AXI or AXI-Lite interfaces.
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默认按已收录数据中的 GitHub 仓库 Stars 排序。Stars 属于来源仓库，同一仓库的多个技能可能共享相同数值；它反映仓库关注度，不代表单个技能的安装量或质量评分。