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MameMame777 AI Skills

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Browse published AI skills maintained by MameMame777. Compare skill descriptions and follow each source repository for setup instructions.

Author statistics

Indexed skills

12

Repository stars across indexed skills

0

Repository forks

0

Average repository stars per indexed skill

0

Repository stars may repeat across skills from the same repository.

12 skills

Browse skills

GitHub

skill-creator

MameMame777

Guide for creating effective skills. This skill should be used when users want to create a new skill (or update an existing skill) that extends Claude's capabilities with specialized knowledge, workflows, or to...

GitHub

skill-creator

MameMame777

Guide for creating effective skills. This skill should be used when users want to create a new skill (or update an existing skill) that extends Claude's capabilities with specialized knowledge, workflows, or to...

GitHub

mcp-workflow

MameMame777

FastMCP + DSIM workflow for UVM test execution. Use when compiling tests, running simulations, executing regression suites, or troubleshooting MCP integration.

GitHub

mcp-workflow

MameMame777

FastMCP + DSIM workflow for UVM test execution. Use when compiling tests, running simulations, executing regression suites, or troubleshooting MCP integration.

GitHub

assertion-design

MameMame777

SystemVerilog Assertions (SVA) as executable specifications. Use when defining timing requirements, protocol specifications, or formal properties for RTL verification.

GitHub

uvm-verification

MameMame777

UVM testbench architecture and verification methodology for SystemVerilog. Use when creating UVM tests, agents, drivers, monitors, sequences, or scoreboards.

GitHub

uvm-verification

MameMame777

UVM testbench architecture and verification methodology for SystemVerilog. Use when creating UVM tests, agents, drivers, monitors, sequences, or scoreboards.

GitHub

assertion-design

MameMame777

SystemVerilog Assertions (SVA) as executable specifications. Use when defining timing requirements, protocol specifications, or formal properties for RTL verification.

GitHub

rtl-debugging

MameMame777

RTL design debugging methodology and reasoning process. Use when investigating test failures, assertion violations, scoreboard mismatches, or analyzing verification results to identify RTL bugs.

GitHub

python-debugging

MameMame777

Python debugging methodology and problem-solving framework. Use when investigating exceptions, async issues, logging problems, or MCP integration failures in Python code.

GitHub

dsim-debugging

MameMame777

DSIM simulator debugging and troubleshooting. Use when investigating compilation errors, runtime failures, waveform analysis, or DSIM environment issues.

GitHub

dsim-debugging

MameMame777

DSIM simulator debugging and troubleshooting. Use when investigating compilation errors, runtime failures, waveform analysis, or DSIM environment issues.

The default order uses GitHub repository stars from our indexed data. Stars belong to the source repository and may be shared by multiple skills. They indicate repository interest, not skill installs or an independent quality score.